The present inventive concept relates to a method of fabricating a semiconductor device. More particularly, the inventive concept relates to a method of fabricating a semiconductor device having a buried gate electrode.
In recent years, research is being conducted on a buried cell array transistor (BCAT) in which a word line (or gate electrode) is buried in a semiconductor substrate.
A BCAT structure allows for word lines to have a pitch (or spacing) of about 0.5 F and helps to minimize the cell area. Also, a buried gate of a BCAT structure may provide a greater effective channel length than a stacked gate or recessed gate. Furthermore, the buried gate of the BCAT structure is advantageous in that it does not yield protrusions. For example, other structures may be easily formed on the semiconductor substrate. In particular, a planarizing process does not have to be carried out after the BCAT structure has been formed. In addition, the forming of the buried gate of the BCAT structure does not require the patterning of a gate electrode. Thus, a SCAT structure facilitates the forming of a metal gate.
One approach that has been considered for burying a word line in a BCAT is to use a chemical vapor deposition (CVD) to form a TiN metal gate in a trench in a substrate. However, this technique has the following problems.
The trench must be rather deep to enable a sub-30 nm 4F2 process because the resistivity of TiN is higher than that desired. Also, the Cl component of the TiCl4 source gas typically used in the CVD process of forming the TiN may penetrate a gate oxide layer and thereby give rise to poor leakage current characteristics of the resulting gate. Furthermore, a TiN buried gate of a cell region may be nonuniformly recessed during the forming of a gate electrode on a peripheral circuit region of a substrate.
Another approach proposes the forming of an additional silicide layer on a TiN metal gate. The desired resistance may be obtained even if the trench in which the TiN is formed is shallow because the silicide layer has a very low resistivity. However, a silicide layer may often have a non-uniform thickness when formed on a narrow layer, i.e., as applied to a gate with a small line width. In this case, deviations in the resistance of word lines are created. Moreover, voids may be formed in a silicide layer when the silicide layer is formed in a narrow trench.